For a nonvolatile memory cell of advanced processes such as Flash EEPROM, due to decreasing dimensions, current of the Cell will change greatly under various process deviation corner. If “1” is defined as a small current and “0” a great current, it is possible that the current of Cell “1” in a fast corner is greater than that of Cell “0” in a slow corner. In order to achieve high reliability, it is required that a trimming datum is set for a reference current of the sense amplifier for different chips. This set requires storing N-bit data into a special cell of the memory, whereas the set datum needs to be retrieved when the set is read, thus resulting in deadlock. Common solutions are as below:
1. A polycrystalline fuse is adopted, as shown in FIG. 1. Number of PAD will be increased by this solution, thus increasing area of the chip and the test cost as well.
2. Laser calibration is usually adopted in a dynamic random access memory (DRAM) and a product of an owner chip factory (IDM). For a universal product of an agent factory (Foundry), this method is seldom adopted due to significant increase of test equipment investment and test cost.
3. A differential nonvolatile memory is adopted, as shown in FIG. 2, such as a nonvolatile static random access memory (nonvolatile SRAM). That is, a new circuit module outside and independent of the nonvolatile memory module stores each data bit using two physical cells based on the differential principle, with the storage results contrary to each other. The additional storage module that this solution introduces will increase the chip area, and an additional test on this module is required during test of a silicon chip as well, thus increasing the test cost.